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| author | Greg Brown <greg.brown@cl.cam.ac.uk> | 2021-12-20 17:52:29 +0000 |
|---|---|---|
| committer | Greg Brown <greg.brown@cl.cam.ac.uk> | 2021-12-20 17:52:29 +0000 |
| commit | 55e7c3cd0f2c3213bf36a2e6dadc1f26dcb877b5 (patch) | |
| tree | 6b52187e4aba6aab4b7b92592764cd9ce5fb3028 /src/Helium/Instructions.agda | |
| parent | d06b8c0a651f101a03ac2efca7cbc3cad0f4496f (diff) | |
Define vmul.
Diffstat (limited to 'src/Helium/Instructions.agda')
| -rw-r--r-- | src/Helium/Instructions.agda | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/src/Helium/Instructions.agda b/src/Helium/Instructions.agda index 2baf39d..9560cc2 100644 --- a/src/Helium/Instructions.agda +++ b/src/Helium/Instructions.agda @@ -64,3 +64,28 @@ module VHSub elem*esize≡32 record { size = zero } = refl elem*esize≡32 record { size = (suc zero) } = refl elem*esize≡32 record { size = (suc (suc zero)) } = refl + +module VMul + where + + record VMul : Set where + field + size : Fin 3 + dest : VecReg + src₁ : VecReg + src₂ : GenReg ⊎ VecReg + + esize : VMul → Fin 33 + esize record { size = zero } = # 8 + esize record { size = (suc zero) } = # 16 + esize record { size = (suc (suc zero)) } = # 32 + + elements : VMul → Fin 5 + elements record { size = zero } = # 4 + elements record { size = (suc zero) } = # 2 + elements record { size = (suc (suc zero)) } = # 1 + + elem*esize≡32 : ∀ d → toℕ (elements d) * toℕ (esize d) ≡ 32 + elem*esize≡32 record { size = zero } = refl + elem*esize≡32 record { size = (suc zero) } = refl + elem*esize≡32 record { size = (suc (suc zero)) } = refl |