Minor tweaks and missing bib entries.

2 files changed, 36 insertions, 5 deletions

diff --git a/thesis.bib b/thesis.bib
index 0222b9c..a1afb24 100644
--- a/thesis.bib
+++ b/thesis.bib
@@ -167,3 +167,33 @@ url = "https://agda.readthedocs.io/en/v2.6.2.1/",
 version = "59c7944b",
 urldate = "2022-05-18T16:39:44+01:00"
 }
+
+@article{10.1145/3290384,
+author = {Armstrong, Alasdair and Bauereiss, Thomas and Campbell, Brian and Reid, Alastair and Gray, Kathryn E. and Norton, Robert M. and Mundkur, Prashanth and Wassell, Mark and French, Jon and Pulte, Christopher and Flur, Shaked and Stark, Ian and Krishnaswami, Neel and Sewell, Peter},
+title = {ISA Semantics for ARMv8-a, RISC-v, and CHERI-MIPS},
+issue_date = {January 2019},
+publisher = {Association for Computing Machinery},
+address = {New York, NY, USA},
+volume = {3},
+number = {POPL},
+url = {https://doi.org/10.1145/3290384},
+doi = {10.1145/3290384},
+abstract = { Architecture specifications notionally define the fundamental interface between hardware and software: the envelope of allowed behaviour for processor implementations, and the basic assumptions for software development and verification. But in practice, they are typically prose and pseudocode documents, not rigorous or executable artifacts, leaving software and verification on shaky ground.  In this paper, we present rigorous semantic models for the sequential behaviour of large parts of the mainstream ARMv8-A, RISC-V, and MIPS architectures, and the research CHERI-MIPS architecture, that are complete enough to boot operating systems, variously Linux, FreeBSD, or seL4. Our ARMv8-A models are automatically translated from authoritative ARM-internal definitions, and (in one variant) tested against the ARM Architecture Validation Suite.  We do this using a custom language for ISA semantics, Sail, with a lightweight dependent type system, that supports automatic generation of emulator code in C and OCaml, and automatic generation of proof-assistant definitions for Isabelle, HOL4, and (currently only for MIPS) Coq. We use the former for validation, and to assess specification coverage. To demonstrate the usability of the latter, we prove (in Isabelle) correctness of a purely functional characterisation of ARMv8-A address translation. We moreover integrate the RISC-V model into the RMEM tool for (user-mode) relaxed-memory concurrency exploration. We prove (on paper) the soundness of the core Sail type system.  We thereby take a big step towards making the architectural abstraction actually well-defined, establishing foundations for verification and reasoning. },
+journal = {Proc. ACM Program. Lang.},
+date = {2019-01},
+articleno = {71},
+numpages = {31},
+keywords = {Theorem Proving, Instruction Set Architectures, Semantics}
+}
+
+@manual{riscv/spec-20191213,
+title = {The RISC-V Instruction Set Manual},
+subtitle = {Volume I: Unprivileged ISA},
+author = {{The RISC-V Foundation}},
+shortauthor = {RISC-V},
+editor = {Waterman, Andrew and Asanović, Krste},
+date = {2019-12-13},
+version = {20191213},
+organsization = {The RISC-V Foundation},
+url = {https://github.com/riscv/riscv-isa-manual/releases/download/Ratified-IMAFDQC/riscv-spec-20191213.pdf},
+}
diff --git a/thesis.org b/thesis.org
index 2e96479..ce00e0d 100644
--- a/thesis.org
+++ b/thesis.org
@@ -35,6 +35,9 @@
 
 #+latex_compiler: pdflatex
 
+
+#+latex_header: \newunicodechar{ʳ}{\ensuremath{^\texttt{r}}}
+#+latex_header: \newunicodechar{ˡ}{\ensuremath{^\texttt{l}}}
 #+latex_header: \newunicodechar{Γ}{\ensuremath{\Gamma}}
 #+latex_header: \newunicodechar{Δ}{\ensuremath{\Delta}}
 #+latex_header: \newunicodechar{Κ}{\ensuremath{K}}
@@ -44,15 +47,12 @@
 #+latex_header: \newunicodechar{ε}{\ensuremath{\epsilon}}
 #+latex_header: \newunicodechar{λ}{\ensuremath{\lambda}}
 #+latex_header: \newunicodechar{σ}{\ensuremath{\sigma}}
-#+latex_header: \newunicodechar{ˡ}{\ensuremath{^\texttt{l}}}
-#+latex_header: \newunicodechar{ʳ}{\ensuremath{^\texttt{r}}}
 #+latex_header: \newunicodechar{ᵗ}{\ensuremath{^\texttt{t}}}
 #+latex_header: \newunicodechar{′}{\ensuremath{'}}
 #+latex_header: \newunicodechar{₁}{\ensuremath{_1}}
 #+latex_header: \newunicodechar{₂}{\ensuremath{_2}}
 #+latex_header: \newunicodechar{ₛ}{\ensuremath{_\texttt{s}}}
 #+latex_header: \newunicodechar{ₜ}{\ensuremath{_\texttt{t}}}
-
 #+latex_header: \newunicodechar{ℓ}{l}
 #+latex_header: \newunicodechar{ℕ}{\ensuremath{\mathbb{N}}}
 #+latex_header: \newunicodechar{ℚ}{\ensuremath{\mathbb{Q}}}
@@ -74,6 +74,7 @@
 #+latex_header: \newunicodechar{≢}{\ensuremath{\not\equiv}}
 #+latex_header: \newunicodechar{⊆}{\ensuremath{\subseteq}}
 #+latex_header: \newunicodechar{⊎}{\ensuremath{\uplus}}
+#+latex_header: \newunicodechar{⊔}{\ensuremath{\sqcup}}
 #+latex_header: \newunicodechar{⊤}{\ensuremath{\top}}
 #+latex_header: \newunicodechar{⊥}{\ensuremath{\bot}}
 #+latex_header: \newunicodechar{⌊}{\ensuremath{\lfloor}}
@@ -231,7 +232,7 @@ xyz
 #+latex: \fi
 #+latex: \cleardoublepage
 
-#+toc: headlines 4
+#+toc: headlines 2
 # #+toc: listings
 # #+toc: tables
 
@@ -539,7 +540,7 @@ defined using a record [cite:@agda.readthedocs.io p.
 be used to define a setoid-enriched monoid:
 
 #+begin_src agda2
-record Monoid ℓ₁ ℓ₂ : Set (ℓsuc (ℓ₁ \lub ℓ₂)) where
+record Monoid ℓ₁ ℓ₂ : Set (ℓsuc (ℓ₁ ⊔ ℓ₂)) where
   infixl 5 _∙_
   infix 4 _≈_
   field